Types & Values

Single-bit types

std_logic

The most common type. Nine possible states defined by IEEE 1164:

Value	Meaning
'0'	Driven low
'1'	Driven high
'Z'	High impedance (tri-state)
'X'	Unknown / conflict
'U'	Uninitialized (default)
'W'	Weak unknown
'L'	Weak low
'H'	Weak high
'-'	Don’t care

signal clk : std_logic := '0';

Requires: library ieee; use ieee.std_logic_1164.all;

bit

Simple two-state logic: '0' or '1'.

signal flag : bit := '0';

boolean

signal done : boolean := false;

Vector types

std_logic_vector

An array of std_logic bits. Declared with a range:

-- MSB-first (most common)
signal data : std_logic_vector(7 downto 0) := x"00";

-- LSB-first
signal addr : std_logic_vector(0 to 3) := "0000";

Accessing bits

-- Single bit
signal msb : std_logic;
msb <= data(7);

-- Slice
signal upper : std_logic_vector(7 downto 4);
upper <= data(7 downto 4);

Concatenation

Combine signals with &:

signal full : std_logic_vector(7 downto 0);
full <= upper & lower;

Numeric types

integer

32-bit signed integer.

signal count : integer := 0;

Literals

Syntax	Type	Example
'0', '1'	bit / std_logic	clk <= '1';
"10101010"	binary vector	data <= "10101010";
x"FF"	hex vector	data <= x"FF";
42	integer	count <= 42;
true, false	boolean	done <= true;

Default values

If you don’t assign an initial value, std_logic signals start as 'U' (uninitialized). This shows up as orange in the waveform viewer. Assign defaults to avoid surprises:

signal clk  : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := x"00";