Known Limitations

nexsim is under active development. The following features are not yet supported but are planned for future releases.

Language features

• Variables — only signals are supported; variable declarations are not recognized
• Loops — for and while loops are not yet implemented
• Functions and procedures — subprogram declarations and calls
• Assert and report — assert statements for self-checking testbenches
• Generate statements — for generate and if generate for structural repetition
• Generics and constants — parameterized entities

Arithmetic and comparison

• +, -, *, /, mod, rem
• <, <=, >, >=
• Shift and rotate operators (sll, srl, sla, sra, rol, ror)

Since arithmetic operators aren’t available yet, designs that use numeric_std operations (counters, adders, ALUs) cannot be simulated.

Libraries

• ieee.numeric_std — unsigned, signed, to_integer(), to_unsigned()
• User-defined packages

Types

• Records and custom types
• Multidimensional arrays
• Subtypes and aliases
• Physical types (beyond time)

Timing

• wait on (signal sensitivity without time)
• wait until (condition-based waiting)
• after clauses for delayed signal assignments
• Transport vs inertial delay models

Attributes

• Signal attributes: 'event, 'stable, 'last_value
• Array attributes: 'left, 'right, 'high, 'low, 'range, 'length

The lack of 'event means rising/falling edge detection (if clk'event and clk = '1') is not yet possible.

Workarounds

For designs that would normally use unsupported features:

• Counters — use std_logic_vector with manual increment logic (once arithmetic is added)
• Clock edge detection — use sensitivity lists with wait for to simulate clock-like behavior
• Self-checking testbenches — visually verify results in the waveform viewer instead of using assert

Check Supported Features for the complete matrix of what works today.