nexsim supports a focused subset of VHDL for behavioral simulation. This page is the definitive reference for what works today.
| Feature | Supported |
|---|
| Entity declarations with ports | Yes |
| Architecture bodies | Yes |
| Component instantiation (hierarchical designs) | Yes |
| Port maps with named association | Yes |
library ieee; use ieee.std_logic_1164.all; | Yes |
| Generics and constants | No |
| Configuration declarations | No |
| Generate statements | No |
| Block statements | No |
| User-defined packages | No |
| Type | Supported |
|---|
std_logic | Yes |
std_logic_vector (with downto and to) | Yes |
bit | Yes |
boolean | Yes |
integer | Yes |
| Records and custom types | No |
| Multidimensional arrays | No |
| Physical types (beyond time) | No |
| Subtypes and aliases | No |
| Feature | Supported |
|---|
| Concurrent signal assignments | Yes |
| Process (with sensitivity list) | Yes |
Process (with wait for) | Yes |
if / elsif / else | Yes |
case / when / others | Yes |
| Signal assignments | Yes |
| Component instantiation | Yes |
| Variables | No |
for / while loops | No |
assert / report | No |
| Functions and procedures | No |
null, return, next, exit | No |
| Operator | Supported |
|---|
and, or, nand, nor, xor, xnor, not | Yes |
=, /= | Yes |
& (concatenation) | Yes |
Indexing: signal(i) | Yes |
Slicing: signal(a downto b) | Yes |
+, -, *, /, mod, rem | No |
<, <=, >, >= | No |
Shift/rotate (sll, srl, etc.) | No |
| Type conversions | No |
| Literal | Supported |
|---|
'0', '1' (bit/std_logic) | Yes |
"10101010" (binary vector) | Yes |
x"FF" (hex vector) | Yes |
Integer (42) | Yes |
| Octal, based, real/float | No |
| Feature | Supported |
|---|
wait for time delays | Yes |
| Delta-cycle simulation | Yes |
| Event-driven scheduling | Yes |
Time units: ns, us, ms | Yes |
wait on / wait until | No |
after clauses | No |
| Transport vs inertial delay | No |
| Feature | Supported |
|---|
Port modes: in, out, inout | Yes |
| Signal initial values | Yes |
| Hierarchical signal resolution | Yes |
| Buffers | No |
| Guarded / resolved signals | No |
| Library | Supported |
|---|
ieee.std_logic_1164 | Yes |
ieee.numeric_std | No |
| User-defined packages | No |
