Examples

Each example below is a complete, self-contained design with testbench. Copy the files and simulate them directly.

2:1 Multiplexer (if statement)

A simple mux that routes one of two inputs to the output based on a select signal.

mux_2x1.vhd

library ieee;
use ieee.std_logic_1164.all;

entity mux_2x1 is
    port(
        in0    : in  std_logic;
        in1    : in  std_logic;
        sel    : in  std_logic;
        output : out std_logic);
end mux_2x1;

architecture behavioral of mux_2x1 is
begin
    process(in0, in1, sel)
    begin
        if (sel = '0') then
            output <= in0;
        else
            output <= in1;
        end if;
    end process;
end behavioral;

mux_2x1_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

entity mux_2x1_tb is
end mux_2x1_tb;

architecture testbench of mux_2x1_tb is
    signal in0_tb    : std_logic;
    signal in1_tb    : std_logic;
    signal sel_tb    : std_logic;
    signal output_tb : std_logic;
begin
    uut: entity work.mux_2x1
        port map (
            in0    => in0_tb,
            in1    => in1_tb,
            sel    => sel_tb,
            output => output_tb
        );

    process
    begin
        in0_tb <= '1'; in1_tb <= '0'; sel_tb <= '0';
        wait for 10 ns;

        in0_tb <= '0'; in1_tb <= '1'; sel_tb <= '0';
        wait for 10 ns;

        in0_tb <= '1'; in1_tb <= '0'; sel_tb <= '1';
        wait for 10 ns;

        in0_tb <= '0'; in1_tb <= '1'; sel_tb <= '1';
        wait for 10 ns;

        wait;
    end process;
end testbench;

nexsim mux_2x1.vhd mux_2x1_tb.vhd --top mux_2x1_tb --run-time 40

2:1 Multiplexer (case statement)

Same mux, written with case instead of if:

mux_case.vhd

library ieee;
use ieee.std_logic_1164.all;

entity mux_2x1_case is
    port(
        in0    : in  std_logic;
        in1    : in  std_logic;
        sel    : in  std_logic;
        output : out std_logic);
end mux_2x1_case;

architecture behavioral of mux_2x1_case is
begin
    process(in0, in1, sel)
    begin
        case sel is
            when '0' =>
                output <= in0;
            when '1' =>
                output <= in1;
            when others =>
                output <= 'X';
        end case;
    end process;
end behavioral;

The when others clause is required for std_logic since it has nine possible values.

Logic Gate Operators

Tests all bitwise operators on two std_logic inputs:

operators_test.vhd

library ieee;
use ieee.std_logic_1164.all;

entity operators_test is
    port(
        a        : in  std_logic;
        b        : in  std_logic;
        and_out  : out std_logic;
        or_out   : out std_logic;
        nand_out : out std_logic;
        nor_out  : out std_logic;
        xor_out  : out std_logic;
        xnor_out : out std_logic;
        not_a    : out std_logic);
end operators_test;

architecture behavioral of operators_test is
begin
    and_out  <= a and b;
    or_out   <= a or b;
    nand_out <= a nand b;
    nor_out  <= a nor b;
    xor_out  <= a xor b;
    xnor_out <= a xnor b;
    not_a    <= not a;
end behavioral;

operators_test_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

entity operators_test_tb is
end operators_test_tb;

architecture testbench of operators_test_tb is
    signal a_tb, b_tb : std_logic;
    signal and_tb, or_tb, nand_tb, nor_tb : std_logic;
    signal xor_tb, xnor_tb, not_tb : std_logic;
begin
    uut: entity work.operators_test
        port map (
            a => a_tb, b => b_tb,
            and_out => and_tb, or_out => or_tb,
            nand_out => nand_tb, nor_out => nor_tb,
            xor_out => xor_tb, xnor_out => xnor_tb,
            not_a => not_tb
        );

    process
    begin
        a_tb <= '0'; b_tb <= '0'; wait for 10 ns;
        a_tb <= '0'; b_tb <= '1'; wait for 10 ns;
        a_tb <= '1'; b_tb <= '0'; wait for 10 ns;
        a_tb <= '1'; b_tb <= '1'; wait for 10 ns;
        wait;
    end process;
end testbench;

nexsim operators_test.vhd operators_test_tb.vhd --top operators_test_tb --run-time 40

Vector Slicing

Demonstrates indexing and slicing std_logic_vector signals:

vector_slicing.vhd

library ieee;
use ieee.std_logic_1164.all;

entity vector_slicing is
    port(
        data_in    : in  std_logic_vector(7 downto 0);
        upper_half : out std_logic_vector(3 downto 0);
        lower_half : out std_logic_vector(3 downto 0);
        msb        : out std_logic;
        lsb        : out std_logic);
end vector_slicing;

architecture behavioral of vector_slicing is
begin
    upper_half <= data_in(7 downto 4);
    lower_half <= data_in(3 downto 0);
    msb        <= data_in(7);
    lsb        <= data_in(0);
end behavioral;

vector_slicing_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

entity vector_slicing_tb is
end vector_slicing_tb;

architecture testbench of vector_slicing_tb is
    signal data_tb  : std_logic_vector(7 downto 0);
    signal upper_tb : std_logic_vector(3 downto 0);
    signal lower_tb : std_logic_vector(3 downto 0);
    signal msb_tb, lsb_tb : std_logic;
begin
    uut: entity work.vector_slicing
        port map (
            data_in    => data_tb,
            upper_half => upper_tb,
            lower_half => lower_tb,
            msb        => msb_tb,
            lsb        => lsb_tb
        );

    process
    begin
        data_tb <= x"A5"; wait for 10 ns;   -- 10100101
        data_tb <= x"F0"; wait for 10 ns;   -- 11110000
        data_tb <= x"0F"; wait for 10 ns;   -- 00001111
        data_tb <= x"FF"; wait for 10 ns;   -- 11111111
        wait;
    end process;
end testbench;

nexsim vector_slicing.vhd vector_slicing_tb.vhd --top vector_slicing_tb --run-time 40