VHDL Basics

If you’re new to VHDL, this page covers the essentials you need to write designs that nexsim can simulate.

Structure of a VHDL file

Every VHDL design has two parts:

1. Entity — declares the interface (ports)
2. Architecture — defines the behavior

library ieee;
use ieee.std_logic_1164.all;

-- Entity: what the module looks like from the outside
entity inverter is
    port(
        a : in  std_logic;
        y : out std_logic
    );
end inverter;

-- Architecture: what the module does
architecture behavioral of inverter is
begin
    y <= not a;
end behavioral;

Ports

Ports define the inputs and outputs of your entity.

port(
    clk    : in  std_logic;                      -- single-bit input
    data   : in  std_logic_vector(7 downto 0);   -- 8-bit input bus
    result : out std_logic;                       -- single-bit output
    bidir  : inout std_logic                      -- bidirectional
);

Port modes:

• in — input only
• out — output only
• inout — bidirectional

Signals

Signals are internal wires declared inside an architecture:

architecture behavioral of my_design is
    signal temp : std_logic := '0';
    signal bus  : std_logic_vector(3 downto 0) := "0000";
begin
    -- use signals here
end behavioral;

Processes

A process is a block of sequential statements. It executes whenever a signal in its sensitivity list changes.

process(a, b, sel)
begin
    if (sel = '0') then
        output <= a;
    else
        output <= b;
    end if;
end process;

For testbenches, processes use wait for instead of a sensitivity list:

process
begin
    data <= '0';
    wait for 10 ns;
    data <= '1';
    wait for 10 ns;
    wait;  -- stop forever
end process;

Concurrent assignments

Outside a process, signal assignments happen concurrently (in parallel):

architecture behavioral of my_design is
begin
    y <= a and b;         -- these two run
    z <= a or b;          -- at the same time
end behavioral;

Component instantiation

To use one entity inside another, instantiate it with a port map:

uut: entity work.inverter
    port map (
        a => input_signal,
        y => output_signal
    );

The work library refers to the current compilation context. All entities you compile together are available under work.

Libraries

nexsim supports the IEEE std_logic_1164 library. Include it at the top of your file:

library ieee;
use ieee.std_logic_1164.all;

This gives you access to std_logic, std_logic_vector, and the standard logic operators.