Quick Start

This guide walks through simulating a 2:1 multiplexer — a small but complete example that shows the full workflow.

The design

Create a file called mux.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity mux_2x1 is
    port(
        in0    : in  std_logic;
        in1    : in  std_logic;
        sel    : in  std_logic;
        output : out std_logic);
end mux_2x1;

architecture behavioral of mux_2x1 is
begin
    process(in0, in1, sel)
    begin
        if (sel = '0') then
            output <= in0;
        else
            output <= in1;
        end if;
    end process;
end behavioral;

The testbench

Create a file called mux_tb.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity mux_2x1_tb is
end mux_2x1_tb;

architecture testbench of mux_2x1_tb is
    signal in0    : std_logic;
    signal in1    : std_logic;
    signal sel    : std_logic;
    signal output : std_logic;

begin
    -- Instantiate the Unit Under Test (UUT)
    uut: entity work.mux_2x1
        port map (
            in0    => in0,
            in1    => in1,
            sel    => sel,
            output => output
        );

    process
    begin
        -- Test case 1: sel = '0', should output in0
        in0 <= '1';
        in1 <= '0';
        sel <= '0';
        wait for 10 ns;

        -- Test case 2: sel = '0', should output in0
        in0 <= '0';
        in1 <= '1';
        sel <= '0';
        wait for 10 ns;

        -- Test case 3: sel = '1', should output in1
        in0 <= '1';
        in1 <= '0';
        sel <= '1';
        wait for 10 ns;

        -- Test case 4: sel = '1', should output in1
        in0 <= '0';
        in1 <= '1';
        sel <= '1';
        wait for 10 ns;

        wait;
    end process;

end testbench;

Run it

Web App

1. Open app.nexsim.dev
2. Click the load files button or drag-and-drop. Select both .vhd files
3. IMPORTANT: Select mux_2x1_tb as the top entity
4. Set run time to 40 ns and click Simulate
5. Check signals in the sidebar to view their waveforms

CLI

nexsim mux.vhd mux_tb.vhd --top mux_2x1_tb --run-time 40

This writes output.vcd. To open the result in the nexsim viewer:

nexsim mux.vhd mux_tb.vhd --top mux_2x1_tb --run-time 40 --open nexsim

This uploads the simulation results and opens a shareable link in your browser. You can also use --open gtkwave or --open surfer to launch a local viewer instead.

What just happened

1. Compile — both files were parsed and type-checked
2. Elaborate — mux_2x1_tb was resolved as the top entity, and the mux_2x1 component was instantiated inside it
3. Simulate — the event-driven simulator ran for 40 ns, executing the testbench process
4. Output — signal changes were recorded and either displayed in the viewer or written to VCD

Next steps

• Using the web app — full walkthrough of the browser interface
• Writing testbenches — patterns for driving and verifying designs
• More examples — multiplexers, encoders, vector operations, and more