Introduction

New to chip design? Learn how it works

Before a chip is manufactured, engineers need to verify that the design actually works. The process looks roughly like this:

1. Describe the circuit — You write code in a hardware description language (HDL) like VHDL. This code defines what your circuit does: its inputs, outputs, and logic.
2. Write a testbench — A testbench is a separate piece of code that feeds inputs into your design and checks the outputs. Think of it as a test suite for hardware.
3. Simulate — A simulator reads your design and testbench, then steps through time tick by tick, computing what every signal would do in a real circuit. No physical chip is needed.
4. Inspect waveforms — The simulator produces a timeline of every signal. You look at these waveforms to verify that your design behaves correctly.
5. Iterate — Fix bugs, re-simulate, repeat — until the design is correct and ready for synthesis onto a real chip or FPGA.

nexsim handles steps 3 and 4. You give it VHDL source files, it simulates your design, and you inspect the results as waveforms — all from a single tool.

What you can do

1. Write VHDL designs and testbenches
2. Simulate them with a single command or a few clicks
3. View signal waveforms over time in the built-in viewer
4. Export results as VCD files for use within nexsim or other clients like GTKWave or Surfer
5. Share simulations via a link

Three ways to use it

	Best for
Web App — app.nexsim.dev	Getting started fast. No install required.
Desktop App — download	Simulation engine runs natively instead of in browser
CLI — nexsim command	Agent use, Scripting, CI pipelines, headless batch runs.

All three use the same simulation engine — your results will be identical regardless of which you choose.

Who it’s for

• Students learning digital design and VHDL
• Engineers prototyping combinational and sequential logic
• Anyone who wants a fast, self-contained VHDL simulator without installing a full EDA suite

Next steps

• Install nexsim
• Run your first simulation