Write VHDL
Author your design and testbench files. nexsim supports entities, architectures, processes, std_logic, vectors, and more.
nexsim docs
Simulate and visualize VHDL waveforms in your browser, on your desktop, or headless via CLI.
Simulate
Compile, elaborate, and run your design. nexsim handles parsing, type checking, and event-driven simulation automatically.
View Waveforms
Inspect signal transitions over time with the built-in waveform viewer. Zoom, pan, place cursors, and read values.
Share Results
Share your simulation with a link. Recipients can view waveforms without re-running anything.